It is known that the market for non-volatile memories, for example of the EEPROM or Flash EEPROM type, is currently growing significantly and the most promising applications relate to the “data storage” field. Until a few years ago, such a market almost exclusively involved the consumer field of digital cameras, with the associated memory cards, or the known USB keys which represented expansion mobile memories for personal computers. Therefore, the demand for these products by the consumer market was mainly addressed to flash memories of large capacity.
This trend seems to be destined to be reinforced in the next years by virtue of the newer and newer applications of portable electronic devices which require a higher and higher memory capacity, for example, for digital cameras or for mobile phones of the last generation operating, for example, according to the 3 G or UMTS standard.
These applications are completely compatible with the natural evolution of Flash memories if one considers that such memories are substantially solid-state mass memory units with further advantages linked to their low power consumption, to their operation silence, and to their reduced space, etc.
As it is well known to the skilled person in the art, the Flash memory architectures are substantially referred to two fundamental paths, the first of which refers to the traditional and widely tested NOR architectures, whereas the second one refers to the more innovative and promising NAND architectures. For the previously cited applications the flash architecture being most suitable to the requirements of low consumption, high density, high program and/or erase speed, is certainly that of the NAND type. This kind of architecture exhibits advantages with respect to NOR architectures. In particular Flash memories with the NAND architecture are faster in the data storage activities and in managing large amounts of data to be restored in a synchronous way, and this makes them more suitable to the use for applications on portable electronic devices.
Since in the data storage applications the need of a random access time is less important with respect to the case of “code storage” applications, the most significant feature of the architectures of the NOR type loses most of its importance to the advantage of the NAND architecture which allows treating large amounts of “synchronous” data in reading and programming in a simple and quick way. However, although having the feature of a superior data modify speed, such NAND memories do not allow a fast random access to the same, since they are oriented to readings of entire pages of at least 512 bytes, but not of the single bytes. In fact, the NAND access protocol is quite slow in random access due to the known latency time, and it exhibits serious difficulties for acceding into a sector or a page in a random way.
For meeting the increasing needs of portable electronic devices it would be necessary to have in a same memory also an excellent random access time, such as to perform the code or the boot of the operative system or of the programs without the burdensome assistance of a RAM. Recently, further new needs have arisen linked to the game and cellular phone markets, which need the availability of high capacity memories, to store any kind of data, but also to store an operative system, video, programs, results etc.
To meet these needs the known technique has recently been proposed including devices defined as MCP (Multi Chip Package) which incorporate, in a single package, different integrated electronic circuits such as for example several types of memory circuits, for example one Flash memory of the NAND type, one of the NOR type, and one RAM memory.
All these memories are assembled and supplied in a single package so as to provide a single device simultaneously having the advantages of all the memories on the market, for example density and storage capability as regards to the NAND portion, or access speed and XIP possibility as regards to the NOR portion, and random access as regards the RAM portion.
One of these devices is commercially known with the acronym OneNAND and manufactured by Samsung. Another example of this kind of Multi Chip Package is the “DiskOnChip” of M-System.
Although advantageous under several aspects, these devices are not exempt from drawbacks. First of all it is to be considered that the various memory circuits to be assembled in a single package are realized with different technologies that oblige addressing problems of compatibility in the supplies on a single package and in the management of the input/output signals.
Secondly, the costs of the resulting package cannot differ significantly from the global cost of the various components, since they cannot exploit large scale economies in the realization of devices assembled with components being different from one another.
There exist, then, a series of problems to be faced starting from the assumption that only a detailed comprehension of the phenomena apt to the memorization of the data inside the memory cells can allow understanding of the intrinsic limits of the adopted technology.
For example, in the herewith attached FIG. 1 the structure is shown of a non-volatile memory device 1 integrated on a semiconductor and comprising a NAND memory matrix 2 of the traditional non-volatile type made of a plurality of blocks or physical sectors organized in cell rows and columns. This type of architecture provides a very organized structure of memory cells divided in two sub-matrixes 3 and 4, left L and right R, making reference to a single row decoding block 5 centrally arranged in the device 1. A bank of registers of the read amplifiers or sense amplifiers 6 and 7 corresponds to each sub-matrix L, R.
In FIG. 1A, by way of illustration only, the matrix 2 is shown with blocks i and j of only four rows, which, however, are practically made of at least 16 rows and four columns. Each row or word line ROW <0:3> of a given n-th block of the matrix corresponds to a respective row driver.
It can be also appreciated that the cells of a given block or sector i, j . . . have a common source line and they are connected to a respective bit line and to the common source line by way of respective drain (DSL) and source (SSL) selectors.
In summary, in the architectures of the traditional type the word lines of a matrix, both of the NOR type and of the NAND type, are independent from each other and the potential for selecting the cell to be read or programmed is applied to only one matrix row. This approach necessarily implies dedicated decoding networks for each sector with an increase in the number of lines and of transistors.
This field suffers from the length of the memory cell arrays which require high propagation times in the reading step for allowing reaching the cells being farthest from the node to which the reading potential is applied. Moreover, it is also to be noted that the lithographic sizes for the manufacturing of non-volatile memories have reached limits lower than about 65 nm, or even than 32 nm, such as to make not only the construction of the interface between the decoding circuitry and the matrix of the cells themselves difficult, but also such as to enormously increase the propagation times of the signals due to the lines length.
In this respect, an important role is played by the row decoding, whose architecture largely conditions both the sizes, and the access time of the memory. This is particularly true where the row lines reach the extreme compactness levels, mainly in Flash of the NAND type, the problem becomes extreme and the implementation complex to such an extent as to make the area occupation inefficient.
The program and erase operations occur by exploiting the Fowler-Nordheim phenomenon, while the reading is an operation of the dynamic type. Well, even due to this the reading step is slowed down a lot.
It is to be remembered that in a sector of the NAND type the smallest erase unit is made of a group of word lines equal to the number of cells of the stack included between the SSL and DSL lines which intercept them, i.e. 16 or 32 according to the memory sizes.
This implies that each stack elemental structure has a very reduced conductivity being thus a great limitation to the reading speed. The conventional stack structure (16,32 cells) is thus intimately slow since it is not very conductive.
Finally, it is to be signaled that current NAND memories do not allow performing an operative code, for example of the XIP type, since the random access time typical of these architectures is on the order of 10-20 usec. The reason of such slowness is due to the particular organization of the matrix which normally comprises groups of 16/32 cells in series which strongly reduces its conductivity, connected to each other through long selector lines which significantly decreases their propagations with long bit-lines which strongly burden the load.
The increase of the load due to the BL is significantly greater than in the corresponding NOR-Flash since in the NAND-Flash the generic BL collects the capacitances of all the stack or column structures which, combined with the large capacitances of the memory, remarkably increase its value.